1. Field of the Invention
The present invention relates to a semiconductor memory device and method of manufacturing the same, and more particularly, to a static random access memory cell having a reduced cell size and method of manufacturing the same.
2. Discussion of Related Art
A SRAM is a significant memory device due to its high speed, low power consumption, and simple operation. The memory cell of the SRAM is constituted of flip-flop circuit. In addition, unlike a DRAM, the SRAM does not need to regularly refresh the stored data and has a straight forward design. The SRAM cell includes: two pull-up devices; two access devices; and two pull-down devices. The SRAM cell is further classified as a full CMOS cell, a high road resistor (HRL), or thin film transistor (TFT) cell according to the load types of the pull-up device.
The TFT cell utilizes P-channel TFT as the pull-up device and it is being developed in 4 Mb or 16 Mb SRAM cell. The SRAM cell with TFT cell structure has low power consumption and a good stability during a stand-by operation in contrast to the SRAM cell with HRL cell structure. In addition, it has outstanding degree of high integration in contrast to the SRAM cell with the full CMOS cell structure having a bulk structure. As the SRAM cell with TFT cell structure, however, has a complex manufacturing process, the SRAM cell with full CMOS cell structure is manufactured to a higher degree. In contrast to the SRAM cell with TFT cell structure, the SRAM cell with the full CMOS cell structure has the simple manufacturing process. In addition, the SRAM cell with the full CMOS cell structure has high current during its operation and good stability.
FIG. 1 is a conventional circuit diagram of a SRAM cell with full CMOS cell structure. In FIG. 1, WL denotes a word line, and BL1 and BL2 denote bit lines. N1 and N2 denote nodes, and VDD is a power voltage. VSS is a ground voltage. UT1 and UT2 are pull-up transistors that comprise a P-channel MOS (PMOS) transistor. DT1 and DT2 are pull-down transistors that comprise N channel MOS (NMOS) transistor. AT1 and AT2 are access transistors that comprise the NMOS transistor.
A first CMOS inverter includes the PMOS transistor for use in the pull-up transistor UT1, and the NMOS transistor for use in pull-down transistor DT1. A second CMOS inverter includes the PMOS transistor for use in the pull-up transistor UT2 and the NMOS transistor for use in the pull-down transistor DT2. An output of the first CMOS inverter is connected with an input of the second CMOS inverter at the node N1. An input of the first CMOS inverter is connected with an output of the second CMOS inverter at the node N2. The sources of the NMOS transistors for use in the access transistors AT1 and AT2, are respectively connected to the bit lines BL1 and BL2, drains of the above NMOS transistors respectively connected to the nodes N1 and N2, and gates the above NMOS transistors respectively connected to the word line WL.
In the above-described SRAM cell with full CMOS cell structure, however, its unit cell is constituted of four NMOS transistors and two PMOS transistors, so that its cell size is large. Accordingly, as the SRAM cell with full CMOS cell structure has difficulty in reducing the cell size below a predetermined level, and it is difficult to manufacture a highly integrated memory device.
Accordingly, an object of the present invention is to provide an SRAM cell which can reduce the number of transistors constituting a memory cell thereby realizing higher integration of memory device, and a method of manufacturing the same.
To achieve the above objects, a SRAM cell according to the present invention includes: a word line and a bit line; an access device connected to the word and bit lines, wherein in case that the word line is selected, the access device outputs data inputted from the bit line; a pull-up device connected to the access device as well as to a predetermined power voltage, wherein the pull-up device operates in pull-up manner according to data inputted from the access device; and a pull-down device connected to the access device and the pull-up device as well as to a ground, wherein the pull-down device operates in pull-down manner according to data inputted from the access devices.
In this embodiment, the access device is an NMOS transistor, the pull-up device is an NMOS transistor, and the pull-down device is a PMOS transistor.
Furthermore, according to the present invention, there is provided a SRAM cell comprising: a semiconductor substrate, wherein a first and a second conductivity type wells are formed therein, a first active region is defined in the well of the first conductivity type and a second active region is defined in the well of the second conductivity type, by the field oxide layer; a gate insulating layer formed on the first and second active regions; first and second gates formed on the first active region and a third gate formed on the second active region; impurity diffusion regions of the second conductivity type formed in the first active region of both sides of each of the first and second gates, wherein the one of the impurity diffusion regions is a common region; impurity diffusion regions of the first conductivity type formed in the second active region of both sides of the third gate; an intermediate insulating layer formed on the overall substrate and having contact holes which expose predetermined portions of the impurity diffusion regions of the first and second conductivity types, predetermined portions of the second gate adjacent to the common impurity diffusion region of the second conductivity type, and predetermined portions of one side of the third gate; and metal interconnection layers each being in contact to the impurity diffusion regions of the first and second conductivity types and the second and third gates, through the contact holes.
Furthermore, the SRAM cell according to the present invention is fabricated by following process. A semiconductor substrate is provided. A first and a second conductivity type wells are formed in the substrate; Isolating layers are formed to define a first active region in the first conductivity well and a second active region in the second conductivity well. A gate insulating layer is formed on the first and second active regions. First and second gates are formed on the first active region which has the gate insulating layer formed thereon, and a third gate on the second active region which has the gate insulating layer formed thereon. Impurity diffusion regions of the second conductivity type are formed in the first active region of both sides of each of the first and second gates so that the one of the impurity diffusion regions is common between the first and second gates. Impurity diffusion regions of the first conductivity type are formed in the second active region of both sides of the third gate. An intermediate insulating layer is formed on the overall substrate. The intermediate insulating layer is etched to expose predetermined portions of each of the impurity diffusion regions of the first and second conductivity types, a predetermined portion of the second gate adjacent to the common impurity diffusion region of the second conductivity type, and a predetermined portion of the third gate to one side, thereby forming contact holes. A metal layer is deposited to filling the contact holes on the intermediate layer. Metal interconnection layers are formed to contact the impurity diffusion regions of the first and second conductivity types and the second and third gates by patterning the metal layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.